1. Field of the Invention
This invention relates to data processing systems, and more particularly to apparatus for expanding the interrupt capabilities of microprocessors.
2. Description of the Prior Art
Microprocessors in general can accept a limited number of priority interrupts. As an example, the Motorola 68020 32-bit microprocessor has seven interrupt priority levels. Level 7 is the highest priority; level 0 indicates that no interrupts are requested.
As described in the "MC 68020 32-bit Microprocessor User's Manual-Second Edition", published by Prentice-Hall Inc., exception processing for interrupts is processed, wherein the microprocessor fetches a vector number from the interrupting device and displaying the level number of the interrupt being acknowledged on pins A1-A3 of the address bus. If the vector number is not generated by the interrupting device, then external logic requests automatic vectoring and the processor internally generates a vector number which is determined by the interrupt level number.
However in a data processing system having multiple processors and a large number of peripheral subsystems, the number of priority interrupts provided is too limiting.